LATEST 2018-2019 VLSI PROJECTS


At TECHNOFIST we provide academic projects based on VLSI with latest IEEE papers implementation. Below mentioned are the 2018 list and abstracts on VLSI domain. For synopsis and IEEE papers please visit our head office and get registered.
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2018-2019 LATEST VLSI BASED PROJECTS

  • Here we are publishing a list of various VLSI projects which will be very useful for final year engineering students for various branches. These VLSI projects are interesting and helpful in our real life also. This category consists of VLSI 2018-2019 project list with abstract/synopsis. we do train a student from basic level of vlsi which includes basic vlsi Classes, projects implementation, final project demo and final code explanations. You may just go through this list of projects and get good knowledge on VLSI projects. If you have questions regarding these projects feel free to contct us.

TVO01
EFFICIENT FPGA MAPPING OF PIPELINE SDF FFT CORES

ABSTRACT - The FFT is one of the most widely used algorithms for calculating the Discrete Fourier Transform (DFT) owing to its efficiency in reducing computation time. Fast Fourier Transform (FFT) has been used in a wide range of applications, such as wide-band mobile digital communication system based on Orthogonal Frequency Division Multiplexing (OFDM) principle, where the system implementation is only feasible when the equipment complexity and power consumption are greatly reduced by utilizing a realtime FFT transformer to replace the bank of (de)modulators for each individual sub-carriers. FFT, as an efficient algorithm to compute the Discrete Fourier Transform (DFT), is one of the most important operations in modern digital signal Processing and communication systems. Contact:
 +91-9008001602
 080-40969981

TVO02
DESIGN OF AN 8-BIT PIPELINED RISC PROCESSOR DESIGN USING VERILOG HDL ON FPGA

ABSTRACT - This article describes an 8-bit RISC processor design using Verilog Hardware Description Language (HDL) on FPGA board. The proposed processor is designed using Harvard architecture, having separate instruction and data memory. The salient feature of proposed processor is pipelining, used for improving performance, such that on every clock cycle one instruction will be executed. Another important feature is that instruction set contains only 34 instructions, which is very simple, easy to learn and compact. The proposed processor has 8-bit ALU, Two 8-bit I/O ports, serial-in/serial-out ports, Eight 8-bit general-purpose registers, 4-bit flag register and priority based three vectored interrupts. Another advantage of the proposed processor is that it can execute programs with up to 262,144 instructions long, such that any practical programs can be fitted into it. The proposed processor is physically verified on Xilinx Spartan 3E Starter Board FPGA with 0.0517μs instruction cycle. Contact:
 +91-9008001602
 080-40969981

TVO03
DESIGN OF AN EFFICIENT ARCHITECTURE FOR DATA ENCRYPTION STANDARD BASED ON FPGA IMPLEMENTATION

ABSTRACT - To achieve the goal of secure communication, cryptography is an essential operation. Many applications, including health-monitoring and biometric data based recognition system, need short-term data security. To design short-term security based applications, there is an essential need of high-performance, low cost and area efficient VLSI implementation of lightweight ciphers. Data encryption standard (DES) is well-suited for the implementation of low-cost lightweight cryptography applications. In this paper, we propose an efficient VLSI archi3tecture for DES algorithm based encryption/decryption engine. Depending upon the encryption/decryption needs, the same set of architecture performs both encryption and decryption operations. In the implementation of DES algorithm, a chain of multiplexer-based architecture is used to implement the substitution operations (SBoxes). The proposed architecture is modeled in the VHDL design language and synthesized in the Xilinx Virtex-5 xc5vfx70t field-programmable gate array (FPGA) device. Hardware synthesis result shows that the proposed design utilizes only 1.07 % slice LUTs, 0.31 % slice registers and 29.22 % of bonded IOBs of the FPGA device fabric. Contact:
 +91-9008001602
 080-40969981

TVO04
FPGA IMPLEMENTATION OF CHANNEL EMULATOR FOR TESTING OF WIRELESS AIR INTERFACE USING VHDL

ABSTRACT - Experimental realism of wireless testbeds along with control and repeatability of experiments are some of the prominent fundamental barriers faced by researchers. To overcome these barriers, we are developing a wireless channel emulator that emulates the physical layer and brings about the realism and repeatability in our experiments. Channel emulators are generally used for testing air interface in Wireless Communication. In a laboratory test environment channel emulators replicate real world communication channel that exists between a transmitter and a receiver, it does so by providing a faded representation of the signal transmitted by the transmitter to the receiver inputs. It can be seen that emulator based approach helps us in understanding the performance of real world wireless channels. It also enables us to test our research in an operational wireless network, along with the advantages of a controlled experimental lab environment. Contact:
 +91-9008001602
 080-40969981

TVO05
FPGA IMPLEMENTATION OF 32-BIT FLOATING POINT MULTIPLIER WITH CARRY LOOK AHEAD ADDER

ABSTRACT - A large number of computer applications(like Computer Graphics, Control Systems, Modeling System, Simulators etc.) needed floating point arithmetic. However, most of the presently available methods are slow and inefficient because of sequential design however the recent development in the field of programmable logic devices such as FPLA and CPLD opens the new area of parallel and high speed floating point designs. Considering that the synchronous architectures requires that that all clock events happen at the same time over the complete circuit which it not possible due to clock skew also the latency and throughput of the circuit are directly linked to the worst-case delay of the slowest element which increases the delay. Hence this paper presents self-timed carry look ahead adder based implementation of IEEE 754 32 bit floating point multiplier for FPGA devices. The simulation results shows that the proposed design has lower latency than synchronous design as well as lower power requirements. Contact:
 +91-9008001602
 080-40969981

TVO06
FPGA IMPLEMENTATION OF FFT IP CORE

ABSTRACT - In this paper, an efficient mapping of the pipeline single-path delay feedback (SDF) fast Fourier transform (FFT) architecture to field-programmable gate arrays (FPGAs) is proposed. By considering the architectural features of the target FPGA, significantly better implementation results are obtained. This is illustrated by mapping an R22SDF 1024-point FFT core toward both Xilinx Virtex-4 and Virtex6 devices. The optimized FPGA mapping is explored in detail. Algorithmic transformations that allow a better mapping are proposed, resulting in implementation achievements that by far outperforms earlier published work. For Virtex-4, the results show a 350% increase in throughput per slice and 25% reduction in block RAM (BRAM) use, with the same amount of DSP48 resources, compared with the best earlier published result. The resulting Virtex-6 design sees even larger increases in throughput per slice compared with Xilinx FFT IP core, using half as many DSP48E1 blocks and less BRAM resources. The results clearly show that the FPGA mapping is crucial, not only the architecture and algorithm choices. Contact:
 +91-9008001602
 080-40969981

TVO07
FPGA DESIGN AND IMPLEMENTATION OF DIGITAL SWITCHING CONTROLLER FOR DC – DC CONVERTERS

ABSTRACT - DC-DC converters are electronic devices. It’s used whenever there is a need to change DC electrical power from one voltage level to another, in an efficient manner. Unlike an AC voltage DC cannot be just stepped down or stepped up. DC-DC convertor is DC equivalent to a Transformer. Typical applications of DC-DC converters are where 24V (which is used for a 24V device) DC must be stepped down to 12V DC to operate a 12V device. Similarly 12V-3V DC & 5V-2V conversion. Contact:
 +91-9008001602
 080-40969981

TVO08
VLSI IMPLEMENTATION OF A SINGLE – CYCLE PROCESSOR FOR A SUBSET OF THE MIPS ARCHITECTURE IN VERILOG HDL (HARDWARE DESCRIPTION LANGUAGE)

ABSTRACT - Because of rich applications, smart operating systems on cell phones are now being migrated to home appliances like televisions. However, applications that are originally designed to be operated by touch screen are not suitable for televisions with these systems. This paper presents a method to manipulate applications with infrared remote control instead of touch screen on televisions without rewriting the code of these applications or adding extra expense on hardware. The principle of the method is to map keystroke events on the remote control to virtual touch based events according to specific mapping relationship corresponding to each application. Since the mapping relationship is various in each scene within one application, scenes should be recognized with feature information before the mapping process. The feature information and the mapping relationship in each scene have been set up prior to running of the application. When one application is running, the current scene of the application could be identified by scene recognition algorithm, the mapping relationship related to the current scene is able to be acquired, and then keystrokes on the remote control would be mapped to touch based events. The proposed method is tested on a smart television platform, and the result indicates the method can operate most applications by remote control, while the input response delay brought by the event mapping is negligibly less than one millisecond. Contact:
 +91-9008001602
 080-40969981

TVO09
VLSI IMPLEMENTATION OF DEEP NEURAL NETWORK USING INTEGRAL STOCHASTIC COMPUTING

ABSTRACT - The hardware implementation of deep neural networks (DNNs) has recently received tremendous attention: many applications in fact require high-speed operations that suit a hardware implementation. However, numerous elements and complex interconnections are usually required, leading to a large area occupation and copious power consumption. Stochastic computing (SC) has shown promising results for low-power area-efficient hardware implementations, even though existing stochastic algorithms require long streams that cause long latencies. In this paper, we propose an integer form of stochastic computation and introduce some elementary circuits. We then propose an efficient implementation of a DNN based on integral SC. The proposed architecture has been implemented on a Virtex7 field-programmable gate array, resulting in 45% and 62% average reductions in area and latency compared with the best reported architecture in the literature. We also synthesize the circuits in a 65-nm CMOS technology, and we show that the proposed integral stochastic architecture results in up to 21% reduction in energy consumption compared with the binary radix implementation at the same misclassification rate. Due to fault-tolerant nature of stochastic architectures, we also consider a quasi-synchronous implementation that yields 33% reduction in energy consumption with respect to the binary radix implementation without any compromise on performance. Contact:
 +91-9008001602
 080-40969981

TVO10
IMPLEMENTATION OF SIXTH SENSE DEVICE

ABSTRACT - In this paper we present an approach for to create a Sixth Sense device which works of the principles of gesture recognition and image processing to capture, zoom(in and out) and toggle pictures with ease just by the help of colored caps/LED worn on the fingertips of the user. Contact:
 +91-9008001602
 080-40969981

TVO11
IMPLEMENTATION OF THREE LEVEL SECURITY SYSTEM

ABSTRACT - The potential threats coming from viruses, malware, adware and hackers are constant. The last couple of years have seen many massive global companies become hacked and compromised. In some cases, this has led to the theft of sensitive and private information including bank details, addresses etc. with a strong security system in place these intrusions can be stopped before they get anywhere near a company’s private data. This is not just important in terms of confidentiality but for avoiding the expensive fines that are imposed on companies that do not successfully protect customer’s data. The project is an authentication system that validates user for accessing the system only when they have input correct password. The project involves three levels of user authentication. There are varieties of password systems and authentications available. It contains three logins having three different kinds of systems. First one is given the access through the face recognition. Second type of authentication is scan the finger print of the user. By using these three level authentication, there is less chance for hacking. Contact:
 +91-9008001602
 080-40969981

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ABOUT VLSI

This category consists of VLSI 2018 project list with abstract/ABSTRACT.Here we provide latest collection of topics developed using latest embedded technology concepts.Latest VLSI topics,Latest VLSI concept for diplomo,Engineering students,VLSI project centers in Bangalore with high quality training and development.Here is a list of project ideas for VLSI concepts.

Students belonging to third year mini projects or final year projects can use these projects as mini-projects as well as mega-projects. If you have questions regarding these projects feel free to contct us. You may also ask for abstract of a project idea that you have or want to work on.The own projects idea for diploma and Engineering students can also be done here

VLSI

The development of microelectronics spans a time which is even lesser than the average life expectancy of a human, and yet it has seen as many as four generations. Early 60’s saw the low density fabrication processes classified under Small Scale Integration (SSI) in which transistor count was limited to about 10. This rapidly gave way to Medium Scale Integration in the late 60’s when around 100 transistors could be placed on a single chip.

It was the time when the cost of research began to decline and private firms started entering the competition in contrast to the earlier years where the main burden was borne by the military. Transistor-Transistor logic (TTL) offering higher integration densities outlasted other IC families like ECL and became the basis of the first integrated circuit revolution. It was the production of this family that gave impetus to semiconductor giants like Texas Instruments, Fairchild and National Semiconductors. Early seventies marked the growth of transistor count to about 1000 per chip called the Large Scale Integration.

By mid eighties, the transistor count on a single chip had already exceeded 1000 and hence came the age of Very Large Scale Integration or VLSI. Though many improvements have been made and the transistor count is still rising, further names of generations like ULSI are generally avoided. It was during this time when TTL lost the battle to MOS family owing to the same problems that had pushed vacuum tubes into negligence, power dissipation and the limit it imposed on the number of gates that could be placed on a single die.

The second age of Integrated Circuits revolution started with the introduction of the first microprocessor, the 4004 by Intel in 1972 and the 8080 in 1974. Today many companies like Texas Instruments, Infineon, AllianceSemiconductors, Cadence, Synopsys, Celox Networks, Cisco, Micron Tech, National Semiconductors, ST Microelectronics, Qualcomm, Lucent, Mentor Graphics, Analog Devices, Intel, Philips, Motorola and many other firms have been established and are dedicated to the various fields in "VLSI" like Programmable Logic Devices, Hardware Descriptive Languages, Design tools, Embedded Systems etc.

Fabrication Process

Why polysilicon gate? The most significant aspect of using polysilicon as the gate electrode is its ability to be used as a further mask to allow precise definition of source and drain regions. This is achieved with minimum gate to source/drain overlap, which leads to lower overlap capacitances and improved circuit performance.

Procedure: A thick layer of oxide is grown on the wafer surface which is known as field oxide (FOX). It is much thicker than the gate oxide. It acts as shield which protects the underlying substrate from impurities when other processes are being carried out on the wafer. Besides, it also aids in preventing conduction between unrelated transistor source/drains. In fact, the thick FOX can act as a gate oxide for a parasitic MOS transistor. The threshold voltage of this transistor is much higher than that of a regular transistor due to thick field oxide. The high threshold voltage is further ensured by introducing channel-stop diffusion underneath the field oxide, which raises the impurity concentration in the substrate in the areas where transistors are not required.

A window is opened in the field oxide corresponding to the area where the transistor is to be made. A thin highly controlled layer of oxide is deposited where active transistors are desired. This is called gate oxide or thinox. A thick layer of silicon dioxide is required elsewhere to isolate the individual transistors.

The thin gate oxide is etched to open windows for the source and drain diffusions. Ion implantation or diffusion is used for the doping. The former tends to produce shallower junctions which are compatible with fine dimension processes. As the diffusion process occurs in all directions, the deeper a diffusion is the more it spreads laterally. This lateral spread determines the overlap between gate and source/drain regions.

VLSI Design

VLSI chiefly comprises of Front End Design and Back End design these days. While front end design includes digital design using HDL, design verification through simulation and other verification techniques, the design from gates and design for testability, backend design comprises of CMOS library design and its characterization. It also covers the physical design and fault simulation.
While Simple logic gates might be considered as SSI devices and multiplexers and parity encoders as MSI, the world of VLSI is much more diverse. Generally, the entire design procedure follows a step by step approach in which each design step is followed by simulation before actually being put onto the hardware or moving on to the next step.
The major design steps are different levels of abstractions of the device as a whole:

1. Problem Specification: It is more of a high level representation of the system. The major parameters considered at this level are performance, functionality, physical dimensions, fabrication technology and design techniques. It has to be a tradeoff between market requirements, the available technology and the economical viability of the design. The end specifications include the size, speed, power and functionality of the VLSI system.

2. Architecture Definition: Basic specifications like Floating point units, which system to use, like RISC (Reduced Instruction Set Computer) or CISC (Complex Instruction Set Computer), number of ALU’s cache size etc.

3. Functional Design: Defines the major functional units of the system and hence facilitates the identification of interconnect requirements between units, the physical and electrical specifications of each unit. A sort of block diagram is decided upon with the number of inputs, outputs and timing decided upon without any details of the internal structure.

4. Logic Design: The actual logic is developed at this level. Boolean expressions, control flow, word width, register allocation etc. are developed and the outcome is called a Register Transfer Level (RTL) description. This part is implemented either with Hardware Descriptive Languages like VHDL and/or Verilog. Gate minimization techniques are employed to find the simplest, or rather the smallest most effective implementation of the logic.

5. Circuit Design: While the logic design gives the simplified implementation of the logic,the realization of the circuit in the form of a netlist is done in this step. Gates, transistors and interconnects are put in place to make a netlist. This again is a software step and the outcome is checked via simulation.

6. Physical Design: The conversion of the netlist into its geometrical representation is done in this step and the result is called a layout. This step follows some predefined fixed rules like the lambda rules which provide the exact details of the size, ratio and spacing between components.

This step is further divided into sub-steps which are:
6.1 Circuit Partitioning: Because of the huge number of transistors involved, it is not possible to handle the entire circuit all at once due to limitations on computational capabilities and memory requirements. Hence the whole circuit is broken down into blocks which are interconnected.
6.2 Floor Planning and Placement: Choosing the best layout for each block from partitioning step and the overall chip, considering the interconnect area between the blocks, the exact positioning on the chip in order to minimize the area arrangement while meeting the performance constraints through iterative approach are the major design steps taken care of in this step.
6.3 Routing: The quality of placement becomes evident only after this step is completed. Routing involves the completion of the interconnections between modules. This is completed in two steps. First connections are completed between blocks without taking into consideration the exact geometric details of each wire and pin. Then, a detailed routing step completes point to point connections between pins on the blocks.
6.4 Layout Compaction: The smaller the chip size can get, the better it is. The compression of the layout from all directions to minimize the chip area thereby reducing wire lengths, signal delays and overall cost takes place in this design step.
6.5 Extraction and Verification: The circuit is extracted from the layout for comparison with the original netlist, performance verification, and reliability verification and to check the correctness of the layout is done before the final step of packaging.

7. Packaging: The chips are put together on a Printed Circuit Board or a Multi Chip Module to obtain the final finished product.

Initially, design can be done with three different methodologies which provide different levels of freedom of customization to the programmers. The design methods, in increasing order of customization support, which also means increased amount of overhead on the part of the programmer, are FPGA and PLDs, Standard Cell (Semi Custom) and Full Custom Design.

While FPGAs have inbuilt libraries and a board already built with interconnections and blocks already in place; Semi Custom design can allow the placement of blocks in user defined custom fashion with some independence, while most libraries are still available for program development. Full Custom Design adopts a start from scratch approach where the programmer is required to write the whole set of libraries and also has full control over the block development, placement and routing. This also is the same sequence from entry level designing to professional designing.